PM7382-PI View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM7382-PI' PDF : 330 Pages View PDF
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
Pin Name Type
RD[0]
RD[1]
RD[2]
RD[3]
RD[4]
RD[5]
RD[6]
RD[7]
RD[8]
RD[9]
RD[10]
RD[11]
RD[12]
RD[13]
RD[14]
RD[15]
RD[16]
RD[17]
RD[18]
RD[19]
RD[20]
RD[21]
RD[22]
RD[23]
RD[24]
RD[25]
RD[26]
RD[27]
RD[28]
RD[29]
RD[30]
RD[31]
Input
Pin Function
No.
N20 The receive data signals (RD[31:0]) contain the
N22 recovered line data for the 32 independently
M21 timed links in normal mode (PMCTEST set low).
L22 Processing of the receive links is on a priority
L23 basis, in descending order from RD[0] to
K21 RD[31]. Therefore, the highest rate link should
J21 be connected to RD[0] and the lowest to RD[31].
J20
H23
G22
G23
F23
E23
D22
E20
C23
A22
D20
B21
D19
For H-MVIP links, RD[n] contains 32/128 time-
slots, depending on the H-MVIP data rate
configured (2.048 or 8.192 Mbps). When
configured for 2.048 Mbps H-MVIP operation,
RD[31:24], RD[23:16], RD[15:8] and RD[7:0] are
sampled on every 2nd rising edge of RMVCK[3],
RMVCK[2], RMVCK[1] and RMVCK[0]
respectively (at the ¾ point of the bit interval).
When configured for 8.192 Mbps H-MVIP
operation, RD[4m] (0£m£7) are sampled on
every 2nd rising edge of RMV8DC (at the ¾ point
of the bit interval).
B20 For channelised links, RD[n] contains the 24
A19 (T1/J1) or 31 (E1) time-slots that comprise the
A18 channelised link. RCLK[n] must be gapped
A17 during the T1/J1 framing bit position or the E1
A16 frame alignment signal (time-slot 0). The
C16 FREEDM-32P256 uses the location of the gap
D15 to determine the channel alignment on RD[n].
C15 RD[31:0] are sampled on the rising edge of the
B14 corresponding RCLK[31:0].
D13
B13
C12
For unchannelised links, RD[n] contains the
HDLC packet data. For certain transmission
formats, RD[n] may contain place holder bits or
time-slots. RCLK[n] must be externally gapped
during the place holder positions in the RD[n]
stream. The FREEDM-32P256 supports a
maximum data rate of 10 Mbit/s on an individual
RD[31:3] link and a maximum data rate of 51.84
Mbit/s on RD[2:0]. RD[31:0] are sampled on the
rising edge of the corresponding RCLK[31:0].
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 12
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