PSD813F1V
Port C – Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 30):
■ MCU I/O Mode
■ CPLD Output – McellBC7-McellBC0 outputs
can be connected to Port B or Port C.
■ CPLD Input – via the Input Macrocells (IMC)
■ Address In – Additional high address inputs
using the Input Macrocells (IMC).
■ In-System Programming (ISP) – JTAG port
can be enabled for programming/erase of the
PSD device. (See the section entitled
PROGRAMMING IN-CIRCUIT USING THE
JTAG SERIAL INTERFACE, page 71, for
more information on JTAG programming.)
■ Open Drain – Port C pins can be configured in
Open Drain Mode
■ Battery Backup features – PC2 can be
configured as a battery input pin (VSTBY).
PC4 can be configured as a Battery-on Indica-
tor output pin (VBATON), indicating when VCC
is less than VBAT.
Port C does not support Address Out mode, and
therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in
certain MCU interfaces.
Figure 30. Port C Structure
DATA OUT
REG.
DQ
WR
MCELLBC[ 7:0]
READ MUX
P
D
B
DIR REG.
DQ
WR
ENABLE PRODUCT TERM (.OE)
CPLD - INPUT
Note: 1. ISP or battery back-up.
DATA OUT
SPECIAL FUNCTION1
OUTPUT
MUX
DATA IN
OUTPUT
SELECT
ENABLE OUT
INPUT
MACROCELL
1
SPECIAL FUNCTION
PORT C PIN
CONFIGURATION
BIT
AI02888B
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