PSD813F1V-70JT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

PSD813F1V-70JT

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 3.3V

STMicroelectronics 

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PSD813F1V

Input Control Signals

The PSD provides the option to turn off the input

control signals (CNTL0, CNTL1, CNTL2, ALE, and

DBE) to the PLD to save AC power consumption.

These control signals are inputs to the PLD AND

array.

During Power Down Mode, or, if any of them are

not being used as part of the PLD logic equation,

these control signals should be disabled to save

AC power. They will be disconnected from the

PLD AND array by setting bits 2, 3, 4, 5, and 6 to

a ‘1’ in the PMMR2.

Table 32. APD Counter Operation

APD Enable Bit ALE PD Polarity

0

X

1

X

1

1

1

0

ALE Level

X

Pulsing

1

0

APD Counter

Not Counting

Not Counting

Counting (Generates PDN after 15 Clocks)

Counting (Generates PDN after 15 Clocks)

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