PSD813F1V-70JT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD813F1V-70JT
STMicroelectronics
'PSD813F1V-70JT' PDF : 110 Pages View PDF
PSD813F1V
Automatic Power-down (APD) Unit and Power-down Mode
The APD Unit, shown in Figure 33, puts the PSD
into Power-down mode by monitoring the activity
of Address Strobe (ALE/AS, PD0). If the APD Unit
is enabled, as soon as activity on Address Strobe
(ALE/AS, PD0) stops, a four bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), the Power-down (PDN) signal becomes ac-
tive, and the PSD enters Power-down mode, as
discussed next.
Power-down Mode
By default, if you enable the PSD APD unit, Power
Down Mode is automatically enabled. The device
will enter Power Down Mode if the address strobe
(ALE/AS) remains inactive for fifteen CLKIN (pin
PD1) clock periods.
setting the appropriate bits in the PMMR
registers. The blocked signals include MCU
control signals and the common clock
(CLKIN). Note that blocking CLKIN from the
PLDs will not block CLKIN from the APD unit.
– All PSD memories enter Standby Mode and
are drawing standby current. However, the
PLDs and I/O ports do not go into Standby
Mode because you don’t want to have to wait
for the logic and I/O to “wake-up” before their
outputs can change. See Table 28 for Power
Down Mode effects on PSD ports.
– Typical standby current are of the order of the
microampere (see Table 29). These standby
current values assume that there are no
transitions on any PLD input.
The following should be kept in mind when the
PSD is in Power Down Mode:
– If the address strobe starts pulsing again, the
PSD will return to normal operation. The PSD
will also return to normal operation if either the
CSI input returns low or the Reset input
returns high.
Table 28. Power-down Mode’s Effect on Ports
Port Function
Pin Level
MCU I/O
No Change
PLD Out
No Change
– The MCU address/data bus is blocked from all
memories and PLDs.
– Various signals can be blocked (prior to Power
Down Mode) from entering the PLDs by
Address Out
Data Port
Peripheral I/O
Undefined
Tri-State
Tri-State
Figure 33. APD Unit
APD EN
PMMR0 BIT 1=1
TRANSITION
DETECTION
ALE
RESET
CSI
CLKIN
EDGE
DETECT
CLR PD
APD
COUNTER
PD
DISABLE BUS
INTERFACE
EEPROM SELECT
FLASH SELECT
PLD SRAM SELECT
POWER DOWN
(PDN) SELECT
DISABLE
FLASH/EEPROM/SRAM
AI02891
Table 29. PSD Timing and Stand-by Current during Power-down Mode
Mode
PLD Propagation
Memory
Access Recovery Time
Delay
Access Time
to Normal Access
Typical Stand-by Current
5V VCC
3V VCC
Power-down
Normal tPD(1)
No Access
tLVDV
50µA(2)
25µA(2)
Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit.
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0.
65/110
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