PSD813F1V-70JT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

PSD813F1V-70JT

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 3.3V

STMicroelectronics 

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PSD813F1V

RESET TIMING AND DEVICE STATUS AT RESET

Power-On Reset

Warm Reset

Upon Power-up, the PSD requires a Reset (RE-

SET) pulse of duration tNLNH-PO (See Tables 67

and 68 for values) after VCC is steady. During this

period, the device loads internal configurations,

clears some of the registers and sets the Flash

memory or EEPROM into Operating mode. After

the rising edge of Reset (RESET), the PSD re-

mains in the Reset mode for an additional period,

tOPR (See Tables 67 and 68 for values), before the

first memory access is allowed.

The PSD Flash or EEPROM memory is reset to

the READ mode upon power up. The FSi and

EESi select signals along with the write strobe sig-

nal must be in the false state during power-up re-

set for maximum security of the data contents and

to remove the possibility of a byte being written on

the first edge of a write strobe signal. The PSD au-

tomatically prevents write strobes from reaching

the EEPROM memory array for about 5ms (tEEH-

WL). Any Flash memory WRITE cycle initiation is

prevented automatically when VCC is below VLKO.

Once the device is up and running, the device can

be reset with a much shorter pulse of tNLNH (See

Tables 67 and 68 for values). The same tOPR time

is needed before the device is operational after

warm reset. Figure 35 shows the timing of the

power on and warm reset.

I/O Pin, Register and PLD Status at Reset

Table 33., page 70 shows the I/O pin, register and

PLD status during Power On Reset, Warm reset

and Power-down mode. PLD outputs are always

valid during warm reset, and they are valid in Pow-

er On Reset once the internal PSD Configuration

bits are loaded. This loading of PSD is completed

typically long before the VCC ramps up to operat-

ing level. Once the PLD is active, the state of the

outputs are determined by the PSDabel equa-

tions.

Figure 35. Reset (RESET) Timing

VCC

RESET

VCC(min)

tNLNH-PO

Power-On Reset

tOPR

tNLNH

tNLNH-A

Warm Reset

tOPR

AI02866b

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