PSD813F1V-70JT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD813F1V-70JT
STMicroelectronics
'PSD813F1V-70JT' PDF : 110 Pages View PDF
PSD813F1V
Port D – Functionality and Structure
Port D has three I/O pins. See Figure 31 and Fig-
ure 32., page 63. This port does not support Ad-
dress Out mode, and therefore no Control
Register is required. Port D can be configured to
perform one or more of the following functions:
■ MCU I/O Mode
■ CPLD Output – External Chip Select (ECS0-
ECS2)
■ CPLD Input – direct input to the CPLD, no
Input Macrocells (IMC)
■ Slew rate – pins can be set up for fast slew
rate
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
■ PD0 – ALE, as address strobe input
■ PD1 – CLKIN, as clock input to the macrocells
flip-flops and APD counter
■ PD2 – CSI, as active Low chip select input. A
High input will disable the Flash memory,
EEPROM, SRAM and CSIOP.
Figure 31. Port D Structure
DATA OUT
REG.
DQ
WR
ECS[ 2:0]
READ MUX
P
D
B
DATA OUT
OUTPUT
MUX
DATA IN
OUTPUT
SELECT
PORT D PIN
DIR REG.
DQ
WR
ENABLE PRODUCT
TERM (.OE)
CPLD - INPUT
AI02889
62/110
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