RC28F256J3D95 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'RC28F256J3D95' PDF : 66 Pages View PDF
Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
Figure 9: Single Word Asynchronous Read Waveform
Address [A]
CEx [E]
OE# [G]
R1
R2
R3
R8
R9
WE# [W]
R4
R16
R7
R6
R10
Data [D/Q]
R11
R12
R13
BY T E# [F]
R5
RP# [P]
Notes:
1.
CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined as the first edge of
CE0, CE1, or CE2 that disables the device (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and
256-Mb” on page 31).
2.
When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e., Status Register reads,
query reads, or device identifier reads).
Figure 10: 4-Word Asynchronous Page Mode Read Waveform
A[MAX:3] [A]
R1
R2
A[2:1] [A]
CEx [E]
OE# [G]
00
R3
R4
01
10
11
WE# [W]
D[15:0] [Q]
R6
R7
R10
R15
1
2
R8
R10
R9
3
4
R5
RP# [P]
Note: CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined as the first edge of
CE0, CE1, or CE2 that disables the device (see Table 16, “Chip Enable Truth Table for 32-, 64-, 128- and
256-Mb” on page 31).
December 2007
316577-06
Datasheet
25
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