RC28F256J3D95 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'RC28F256J3D95' PDF : 66 Pages View PDF
Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
Table 14: Reset Specifications
#
Symbol
Parameter
Min
Max
Unit
RP# Pulse Low Time
P1
tPLPH
(If RP# is tied to VCC, this specification is not applicable)
RP# High to Reset during Block Erase, Program, or Lock-Bit
P2
tPHRH
Configuration
25
µs
100
ns
Vcc Power Valid to RP# de-assertion (high) 130nm
60
µs
P3
tVCCPH Vcc Power Valid to RP# de-assertion (high) 65nm
300
µs
Notes:
1.
These specifications are valid for all product versions (packages and speeds).
2.
If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RP# Pulse Low Time is 100 ns.
3.
A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are
valid.
Notes
1,2
1,3
7.4
AC Test Conditions
Figure 15: AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
0.0
Test Points
VCCQ/2 Output
Note: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Figure 16: Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Note: CL Includes Jig Capacitance
Figure 17: Test Configuration
Test Configuration
VCCQ = VCCQMIN
CL (pF)
30
Datasheet
30
December 2007
316577-06
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