RS8953SPBEPF View Datasheet(PDF) - Conexant Systems
Part Name
Description
MFG CO.
'RS8953SPBEPF' PDF : 173 Pages View PDF
4.0 Registers
4.15 PRA Transmit Read
RS8953B/8953SPB
HDSL Channel Unit
SA7_MODE
SA8_MODE
E_MODE
Controls the behavior of Sa7 bits, transmitted towards the HDSL link, as follows:
0 = Transparent
1 = From bits buffer 1
Controls the behavior of Sa8 bits transmitted towards the HDSL link, as follows:
0 = Transparent
1 = From bits buffer 1
Controls the behavior of the E-bits transmitted towards the HDSL link, as follows:
Code
00
01
10
11
E-bits
Transparent
From bits buffer 0
Automatic
Illegal
The Automatic mode operates in conjunction with the receiver CRC4 check result (reported
also in RX_PRA_MON0), as follows:
Receiver CRC Check
Error
OK
E-bits Forced to
0
1
NOTE: The value of this register takes effect starting with the next PCM multiframe
following the write access cycle completion.
0x41—PRA Transmit Control Register 1 (TX_PRA_CTRL1)
7
—
PRA_EN
SYNCHR_EN
CRC4_MODE
A_MODE
6
5
RESET_E_CNT
AIS
4
A_MODE
3
2
CRC4_MODE[1:0]
1
SYNCHR_EN
0
PRA_EN
Used to enable or globally disable the receive PRA circuitry, as follows:
0 = Disable ALL RX PRA functionality
1 = Enable ALL RX PRA functionality
Used to enable or disable the PCM multiframe synchronization state machine, as follows:
0 = Enable—Use TMSYNC input pin as a qualifier of the frame, and force
the synchronization state machine to HUNT mode
1 = Disable—Use TMSYNC input as a qualifier of multiframe
CRC4_MODE controls the behavior of the CRC bits transmitted towards the HDSL link, as
follows:
Code
00
01
10
11
CRC4 Bits
Transparent
All 1
Re-calculated
Illegal
Controls the behavior of A-bits transmitted towards the HDSL link, as follows:
0 = Transparent
1 = From bits buffer 0
4-66
Conexant
N8953BDSB
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