RS8953SPBEPF View Datasheet(PDF) - Conexant Systems
Part Name
Description
MFG CO.
'RS8953SPBEPF' PDF : 173 Pages View PDF
RS8953B/8953SPB
HDSL Channel Unit
4.0 Registers
4.16 PRA Transmit Write
4.16 PRA Transmit Write
Table 4-13. PRA Transmit Write Registers
Address
Register Label
Bits
0x70
TX_PRA_CTRL0
8
0x71
TX_PRA_CTRL1
7
0x72
TX_BITS_BUFF1
6
0x73
TX_PRA_TMSYNC_OFFSET
8
0x74
TX_BITS_BUFFO
8
Name/Description
PRA Transmit Control Register 0
PRA Transmit Control Register 1
PRA Transmit Bits Buffer 1
PRA Transmit TMSYNC Offset Register
PRA Transmit Bits Buffer 0
0x70—PRA Transmit Control Register 0 (TX_PRA_CTRL0)
7
6
E_MODE[1:0]
5
SA8_MODE
4
SA7_MODE
3
2
SA6_MODE[1:0]
1
SA5_MODE
0
SA4_MODE
SA4_MODE
SA5_MODE
SA6_MODE
SA7_MODE
Controls the behavior of Sa4 bits transmitted towards the HDSL link, as follows:
0 = Transparent
1 = From bits buffer 1
Controls the behavior of Sa5 bits transmitted towards the HDSL link, as follows:
0 = Transparent
1 = From bits buffer 0
Controls the behavior of Sa6 bits transmitted towards the HDSL link, as follows:
Code
00
01
10
11
Sa6 Bits
Transparent
From bits buffer 0
Automatic
Illegal
The Automatic mode operates based on the result of the receiver (HDSL to PCM) CRC
check and E-bits, as follows:
Received E-bits
0 (Error)
0 (Error)
1 (No Error)
1 (No Error)
Receive CRC Checks
Error
No Error
Error
No Error
Sa6
0011
0001
0010
From bits buffer 0 (sec 0)
NOTE: MSB of Sa6 is transmitted first (i.e., in frames 1 and 9).
Controls the behavior of Sa7 bits transmitted towards the HDSL link, as follows:
0 = Transparent
1 = From bits buffer 1
N8953BDSB
Conexant
4-69
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