SAA7392HL/M2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HL/M2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.8 Digital output
The AES/EBU signal is available on pin EBUOUT,
according to the format defined by the “IEC958
specification”. This signal is only available in the CLV
modes of the decoder (not in QCLV). Three different
modes can be selected:
• EBU off
• EBU data all zero
• EBU data valid.
The EBU interface uses a clock derived from XTLI for
timing generation. For correct operation of the EBU
interface, BCLK must be non-gated and the selected EBU
clock and BCLK must fulfil the following constraint:
EBU clock = WCLK × 64
WCLK is BCLK divided by 16, 24 or 32 depending on the
chosen output format.
7.8.1 INPUT CONFIGURATION REGISTER (INPUTCONFIG)
Table 59 Input Configuration Register (address 1EH) - WRITE
7
6
5
4
3
EBUClkSelect
−
−
−
−
2
ScramOn
1
InputFmt.1
0
InputFmt.0
Table 60 Description of InputConfig bits
BIT
SYMBOL
7
EBUClkSelect
6 to 3
2
1
0
−
ScramOn
InputFmt1
InputFmt0
DESCRIPTION
If EBUClkSelect = 0, then the EBU clock frequency is 1/3fXTLI. If
EBUClkSelect = 1, then the EBU clock frequency is 2/3fXTLI (input
MUXSWI must be a logic 1 for this setting).
These 4 bits are reserved.
See Section 7.11.1.
2000 Mar 21
32
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