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SAA7392HL/M2B View Datasheet(PDF) - Philips Electronics

Part Name
Description
MFG CO.
SAA7392HL/M2B
Philips
Philips Electronics Philips
'SAA7392HL/M2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.8.2 FORMAT
The digital audio output consists of 32-bit words (subframes) transmitted in biphasemark code (two transitions for a
logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384.
Table 61 Digital audio output subframe format
BIT
0 to 3
4 to 7
8 to 27
28
29
30
31
FIELD NAME
sync
auxiliary
audio sample
validity flag
user data
channel status
parity bit
DESCRIPTION
The sync word is formed by violation of the biphase rule and therefore does not
contain any data. Its length is equivalent to 4 data bits. The 3 different sync patterns
indicate the following situations:
Sync B: Start of a block (384 words), word contains left sample
Sync M: Word contains left sample (no block start)
Sync W: Word contains right sample.
These bits are not used; normally zero.
Left and right samples are transmitted alternately. The first 4 bits not used (always
zero); 2’s compliment; LSB = bit 12 and MSB = bit 27.
If validity flag = 1, audio samples are flagged if an error has been detected but was
uncorrectable. This flag remains the same even if data is taken after concealment.
Subcode bits Q until W from the subcode section are transmitted via the user data
bit. This data is asynchronous with the block rate.
The channel status bit is the same for left and right words. Therefore, a block of
384 words contains 192 channel status bits. The category code is always CD. The bit
assignment is shown in Table 62.
Even parity for bits 4 to 30.
Table 62 Channel status bit assignment
BIT
0 to 4
5 to 7
8 to 15
28 to 29
16 to 27,
30 to 191
FIELD NAME
DESCRIPTION
control
Bits 1 to 4 copied from register Output2. Bit 2 is logic 1 when copy permitted. Bit 3 is
logic 1 when recording has pre-emphasis
reserved mode always zero
category code CD: bit 8 = logic 1, all other bits = logic 0
clock accuracy set by register Output2:
10 = level I
00 = level II
01 = level III
remaining
always zero
2000 Mar 21
33
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