SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Preliminary specification
SC2000
SCbus Loopback Mode Select (C_5):
When SCbus Mode is selected (C_4 =
0), this bit controls the SCbus loopback.
Clearing this bit to 0 disables Loopback
Mode. Setting this bit to 1 enables Loop-
back Mode.
When PEB Mode is selected (C_4 = 1)
this bit has no effect.
When loopback is enabled the expan-
sion bus timing and data bus drivers are
forced to high impedance, and the data
outputs are looped back internally to the
corresponding inputs. This mode is used
to test the SC2000 without disrupting
the operation of the SCbus.
A clock must be supplied at CLK_IN
for operation in Loopback Mode.
This bit is cleared on RESET.
PEB Module Type (C_7, C_6): When
PEB Mode is selected (C_4 = 1) this
two-bit field selects the PEB module
type.
When SCbus Mode is selected (C_4 = 0)
these bits have no effect.
These bits are cleared on RESET.
PEB Module Type
C_7, C_6 Operating Mode
00
Resource module without switching
01
Network module without switching
10
Resource module with switching
11
Network module with switching
Configuration Register 2 (01H)
Configuration Register 2
Bit
0
1
2
3
4
5
6
7
Note:
Function
C_8: CLK_IN Divider 0
C_9: CLK_IN Divider 1
C_10: CLK_IN Divider 2
C_11: SYNC_IN Format
C_12: SYNC_IN Select 0
C_13: SYNC_IN Select 1
C_14: PEB Network
Modul Timing Select 0
C_15: PEB Network
Modul Timing Select 1
Bit 0 is the LSB of the Low Byte
Data Register.
CLK_IN Divider (C_10, C_9, C_8):
This field selects the CLK_IN division
ratio used in the generation of the sys-
tem source clock.
When “CLK_IN divide by 1” and SCbus
Mode are selected and the expansion
bus timing drivers are enabled (C_10,
C_9, C_8, C_4, C_1 = 00001), then
SCLKx2* is held high and the FSYNC*
period is equal to 1 SCLK period.
These bits are cleared on RESET.
CLK_IN Divider
C_10, C_9, C_8 CLK_IN Divided By
000
1
001
2
010
4
011
8
100
16
101
Reserved
110
Reserved
111
Reserved
SYNC_IN Format (C_11): This bit
selects the SYNC_IN format to be either
PEB conventional or ST-BUS. If this bit
is cleared to 0 then SYNC_IN is taken to
be in the PEB conventional format. If
this bit is set to 1, SYNC_IN is taken to
be in the ST-BUS format.
In ST-BUS format the CLK_IN signal is
inverted to produce the system clock
source.
This bit is cleared on RESET.
SYNC_IN Select (C_13, C_12):This
two bit field selects the function of
the SYNC_IN input.
These bits are cleared on RESET.
SYNC_IN Select
C_13, C_12
00
01
10
11
SYNC_IN Function
Ignored
Frame sync
Ignored
Multi-frame sync
PEB Network Module Timing Select
(C_15, C_14): When PEB Network
Module Mode is selected (C_6, C_4,
C_1 = 111), this two bit field selects the
module timing mode.
Otherwise these bits have no effect.
These bits are cleared on RESET.
PEB Network Module Timing Mode
C_15, C_14 Timing Mode
00
Master
01
Master, MSYNCTfi
L_MSYNCT
10
Slave, MSYNCTfi
MSYNCR
11
Slave, SYNC_INfi
MSYNCR
Configuration Register 3 (02H)
Configuration Register 3
Bit
0
1
2
3
4
5
6
7
Note:
Function
C_16: Expansion Bus Data
Sample Position
C_17: Local Bus Data
Sample Position
C_18: SCbus Output Driver
C_19: SO Output Driver
C_20: Local Bus Framing Format
C_21: Message Channel
TXD Select
C_22: SERT Mux 0
C_23: SERT Mux 1
Bit 0 is the LSB of the Low Byte
Data Register.
2000 Sep 07
10
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