SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Additional Features
The SO output may be set to high im-
pedance on frame boundaries by setting
the Source Routing Memory Switch
Output Enable Bit. This allows outputs
from multiple devices to be connected
to a common line. The SO signal may
also be configured as an open collector
output.
The data sample position of both local
and external buses is selectable between
50% and 75% of the bit width.
Logical and Physical Pinout Diagrams
SC2000
24
D_7
26
D_6
27
D_5
29
D_4
30
D_3
31
D_2
32
D_1
33
D_0
37
A_1
38
A_0
23
CS*
22
RD*(STRB*)
20
WR*(R/W*)
18
RESET
17
I*(M)
50
CLK_IN
52
SYNC_IN
39
SI
54
TXD
PLCC68
INT
35
(CLKT) SCLKX2*
55
(FSYNCT) SCLK
57
(MSYNCT) RSRVD
58
(SERT) FSYNC*
59
(SIGT) CLKFAIL
61
(L_CLKT) SD_0
62
(L_FSYNCT) SD_1
63
(L_MSYNCT) SD_2
65
(L_TSX*) SD_3
66
(L_SERT) SD_4
67
(L_SIGT) SD_5
1
(CLKR) SD_6
3
(FSYNCR) SD_7
4
(MSYNCR) SD_8
5
(SERR) SD_9
7
(SIGR) SD_10
8
(R_CLKT) SD_11
9
(R_FSYNCT) SD_12
11
(R_MSYNCT) SD_13
12
(R_TSX*) SD_14
13
(R_SERT) SD_15
15
(R_SIGT) MC
16
SO_CLK
41
SI_CLK
40
SO_FS
48
SI_FS
47
SO_MS
46
SI_MS
44
SO
43
RXD
53
Logical Pin Organization
10
SD_12
11
SD_13
12
SD_14
13
14
SD_15
15
MC
16
I*
17
RESET
18
19
WR*
20
21
RD*
22
CS*
23
D_7
24
25
D_6
26
SC2000
68-PIN PLCC
(TOP VIEW)
Physical Pinout
Preliminary specification
SC2000
60
59
FSYNC*
58
RSRVD
57
SCLK
56
55
SCLKX2*
54
TXD
53
RXD
52
SYNC_IN
51
50
CLK_IN
49
48
SO_FS
47
SI_FS
46
SO_MS
45
44
SI_MS
2000 Sep 07
5
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