SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Preliminary specification
SC2000
PIN DESCRIPTION
Pin Name
D_0 - D_7
Input/Output
I/O
A_0, A_1
I
CS*
I
I*
I
RD*
I
or
STRB*
I
WR*
I
or
R/W*
I
RESET
I
CLK_IN
I
SYNC_IN
I
SI
I
SO
O
TXD
I
INT
O
SCLKx2* or
I/O
CLKT
I
SCLK or
I/O
FSYNCT
I
RSRVD or
I
MSYNCT
I
FSYNC* or
I/O
SERT
I
CLKFAIL
I/O
SD_0 or
I/O
L_CLKT
I/O
SD_1 or
I/O
L_FSYNCT
I/O
SD_2 or
I/O
L_MSYNCT
I/O
SD_3 or
I/O
L_TSX*
I/O
Pin Number
33, 32, 31, 30,
29, 27, 26, 24
38, 37
23
17
22
20
18
50
52
39
43
54
35
55
57
58
59
61
62
63
65
66
Pin Description
Data bus.
These bi-directional, tri-state lines are the SC2000s interface to the CPU data bus.
Address bus. These inputs select the internal register used by a read or write operation. Normally connected to CPU address lines
A0 and A1 in 8-bit CPU systems, or A1 and A2 in 16-bit CPU systems.
Chip Select. This active low input selects the chip for a read or write operation.
Bus Interface Mode Select. This input selects Intel- and Motorola-type data bus interface configurations.
0 = Intel. 1 = Motorola.
I* = 0. Read
This active low input enables the data bus drivers to drive the CPU data bus with the contents of the internal register selected by
A_0 and A_1.
I* = 1. Strobe
During a read operation a low on this input enables the data bus drivers to drive the CPU data bus with the contents of the internal
register selected by A_0 and A_1. During a write operation data is transferred from the CPU data bus to the register selected b y
A_0 and A_1 on a low to high transition of this signal.
I* = 0. Write
During a write operation data is transferred from the CPU data bus to the register selected by A_0 and A_1 on a low to high
transition of this signal.
I* = 1. Read/Write
This input selects between a write operation (R/W* = 0) and a read operation (R/W* =1).
Reset.
This active high input forces all outputs to tri-state, and resets the SC2000 chip.
Local clock input.
Local sync input.
Serial input.
Local serial bus data input line.
Serial output.
Local serial bus data output line.
Transmit data
SCbus Message Bus transmit data input line.
Interrupt Request.
Active high interrupt request output line.
Register bit C_4 = 0. SCbus System clock x 2.
Register bit C_4 = 1. PEB Transmit clock.
Register bit C_4 = 0. SCbus System clock.
Register bit C_4 = 1. PEB Frame sync.
Register bit C_4 = 0. SCbus Reserved.
Register bit C_4 = 1. PEB Transmit multi-frame sync.
Register bit C_4 = 0. SCbus Frame sync.
Register bit C_4 = 1. PEB Transmit serial data.
Register bit C_4 = 0.
SCbus Clock fail signal.
Register bit C_4 = 0. SCbus Serial data stream 0.
Register bit C_4 = 1. PEB Local resource transmit clock.
Register bit C_4 = 0. SCbus Serial data stream 1.
Register bit C_4 = 1. PEB Local resource transmit frame sync.
Register bit C_4 = 0. SCbus Serial data stream 2.
Register bit C_4 = 1. PEB Local resource multi-frame sync.
Register bit C_4 = 0. SCbus Serial data stream 3.
Register bit C_4 = 1. PEB Local resource transmit time slot enable.
2000 Sep 07
6
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