SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Preliminary specification
SC2000
REGISTER DESCRIPTION
Terminate (CS_3): Setting this bit to 1
terminates any command that requires
Microprocessor Interface Registers
synchronization with the SC2000’s in-
The four 8-bit Microprocessor Interface ternal state machine. This command is
Registers comprise the command and
needed to complete a command when
control port for the SC2000.
the SC2000’s internal state machine has
Command/Status Register
stopped running due to the failure of the
Busy (CS_0): This bit is automatically
system clocks. The command currently
set to 1 when a command that requires being executed is completed asynchro-
synchronization with the SC2000’s in- nously and the BUSY bit is cleared to 0.
ternal state machine has been initiated. To restore normal operation the TER-
The bit is cleared to 0 when the com- MINATE bit must be explicitly cleared
mand has been completed. The follow- to 0. This bit can be read back for verifi-
ing commands require synchronization: cation purposes.
• Destination Routing Memory Write
• Source Routing Memory Write
• Parallel Access Destination Write
• Parallel Access Source Read
Read (CS_1): Setting this bit to 1 ini-
tiates a read of the register pointed to
by the contents of the Internal Address
Register. Once the BUSY bit is read as
cleared to 0 the contents of the selected
register will be available in the Low Byte
and High Byte Data Registers. Once the
READ operation is complete the READ
bit is cleared automatically.
Write (CS_2): Setting this bit to 1 ini-
tiates a write to the register pointed to
by the contents of the Internal Address
Register. Once the busy bit has been
cleared to 0 the contents of the Low Byte
and High Byte Data Registers have been
transferred into the selected register.
Once the WRITE operation is com-
pleted the WRITE bit is cleared auto-
matically.
BIT
0
1
2
3
4
5
6
7
Note:
Command/Status Register
R/W Command/Status
R
CS_0: Busy (S)
W
CS_1: Read (C)
W
CS_2: Write (C)
R/W CS_3: Terminates (C)
CS_4: Reserved
CS_5: Reserved
CS_6: Reserved
R/W CS_7: Reset (C)
(1) Bit 0 is the LSB of the byte.
(2) Initiating multiple commands in a
single access is not recommended.
CPU Interface Register Map
A_1
A_0
Register Name
0
0
Command/Status
0
1
Internal Address
1
0
Low Byte Data
1
1
High Byte Data
BIT
0
1
2
3
4
5
6
7
Note:
Low Byte Data Register
R/W Function
R/W D_0
R/W D_1
R/W D_2
R/W D_3
R/W D_4
R/W D_5
R/W D_6
R/W D_7
Bit 0 is the LSB of the byte.
BIT
0
1
2
3
4
5
6
7
Note:
High Byte Data Register
R/W Function
R/W D_8
R/W D_9
R/W D_10
R/W D_11
R/W D_12
R/W D_13
R/W D_14
R/W D_15
Bit 0 is the LSB of the byte.
2000 Sep 07
8
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