SPEAR300-2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
SPEAR300-2
STMicroelectronics
'SPEAR300-2' PDF : 83 Pages View PDF
SPEAr300
Figure 3. Clock generator overview
24 MHz
OSC
PLL1
PLL2
Architecture overview
333 MHz CPU_CLK
DIV 2
166 MHz HCLK
DIV 4
83 MHz PCLK
166 MHz
DDR_CLK
32.768 kHz
RTC
PLL3
CLK12MHZ
CLK30MHZ
CLK48MHZ
CLK32MHZ
2.2.2
The multi clock generator block, takes a reference signal (which is usually delivered by the
PLL), generates all clocks for the IPs of SPEAr300 according to dedicated programmable
registers.
Each PLL uses an oscillator input of 24 MHz to generate a clock signal at a frequency
corresponding to the highest of the group. This is the reference signal used by the multi
clock generator block to obtain all the other required clocks for the group. Its main feature is
electromagnetic interference reduction capability.
The user can set up the PLL in order to modulate the VCO with a triangular wave. The
resulting signal has a spectrum (and power) spread over a small programmable range of
frequencies centered on F0 (the VCO frequency), obtaining minimum electromagnetic
emissions. This method replaces all the other traditional methods of EMI reduction, such as
filtering, ferrite beads, chokes, adding power layers and ground planes to PCBs, metal
shielding and so on. This gives the customer appreciable cost savings.
In sleep mode the SPEAr300 runs with the PLL disabled so the available frequency is 24
MHz or a sub-multiple (/2, /4, /8).
Power saving system mode control
Using three mode control bits, the system controller switch the SPEAr300 to any one of four
different modes: DOZE, SLEEP, SLOW and NORMAL.
● SLEEP mode: In this mode the system clocks, HCLK and CPU_CLK, are disabled and
the System Controller clock is driven by a low speed oscillator (nominally 32768 Hz).
When either a FIQ or an IRQ interrupt is generated (through the VIC) the system enters
Doc ID 16324 Rev 2
13/83
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