SPEAR300-2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
SPEAR300-2
STMicroelectronics
'SPEAR300-2' PDF : 83 Pages View PDF
Architecture overview
SPEAr300
DOZE mode. Additionally, the operating mode setting in the system control register
automatically changes from SLEEP to DOZE.
● DOZE mode: In this mode the system clocks, HCLK and CPU_CLK, and the System
Controller clock are driven by a low speed oscillator. The System Controller moves into
SLEEP mode from DOZE mode only when none of the mode control bits are set and
the processor is in Wait-for-interrupt state. If SLOW mode or NORMAL mode is
required the system moves into the XTAL control transition state to initialize the crystal
oscillator.
● SLOW mode: During this mode, both the system clocks and the System Controller
clock are driven by the crystal oscillator. If NORMAL mode is selected, the system goes
into the "PLL control" transition state. If neither the SLOW nor the NORMAL mode
control bits are set, the system goes into the "Switch from XTAL" transition state.
● NORMAL mode: In NORMAL mode, both the system clocks and the System Controller
clock are driven by the PLL output. If the NORMAL mode control bit is not set, then the
system goes into the "Switch from PLL" transition state.
2.3
Vectored interrupt controller (VIC)
The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in
response to peripheral interrupts. There are 32 interrupt lines and the VIC uses a separate
bit position for each interrupt source. Software controls each request line to generate
software interrupts.
2.4
General purpose timers
SPEAr300 provides three general purpose timers (GPTs) acting as APB slaves.
Each GPT consists of 2 channels, each one made up of a programmable 16-bit counter and
a dedicated 8-bit timer clock prescaler. The programmable 8-bit prescaler performs a clock
division by 1 up to 256, and different input frequencies can be chosen through SPEAr300
configuration registers (frequencies ranging from 3.96 Hz to 48 MHz can be synthesized).
Two different modes of operation are available:
● Auto-reload mode, an interrupt source is activated, the counter is automatically cleared
and then it restarts incrementing.
● Single-shot mode, an interrupt source is activated, the counter is stopped and the GPT
is disabled.
2.5
Watchdog timer
The watchdog timer consists of a 32-bit down counter with a programmable timeout interval
that has the capability to generate an interrupt and a reset signal on timing out. The
watchdog module is intended to be used to apply a reset to a system in the event of a
software failure.
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Doc ID 16324 Rev 2
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