SPEAR300-2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
SPEAR300-2
STMicroelectronics
'SPEAR300-2' PDF : 83 Pages View PDF
SPEAr300
Architecture overview
2.11
Flexible static memory controller (FSMC)
SPEAr300 provides a Flexible Static Memory Controller (FSMC) which interfaces the AHB
bus to external NAND/NOR Flash memories and to asynchronous SRAM memories.
Main features:
● Provides an interface between AHB system bus and external parallel memory devices
● Interfaces static memory-mapped devices including RAM, ROM and synchronous burst
Flash.
● For SRAM and Flash 8/16-bit wide, external memory and data paths are provided
● FSMC performs only one access at a time and only one external device is accessed.
● Supports little-endian and big-endian memory architectures
● AHB burst transfer handling to reduce access time to external devices
● Supplies an independent configuration for each memory bank
● Programmable timings to support a wide range of devices
– Programmable wait states (up to 31)
– Programmable bus turnaround cycles (up to 15)
– Programmable output enable and write enable delays (up to 15)
● Provides independent chip select control for each memory bank
● Shares the address bus and the data bus with all the external peripherals. Only the chip
selects are unique for each peripheral
● External asynchronous wait control
2.12
UART
Main features:
● Hardware/software flow control
● Modem control signals
● Separate 16 x 8 (16 locations deep x 8-bit wide) transmit and 16 x 12 receive FIFOs to
reduce CPU interrupts
● Speed up to 3 Mbps.
2.13
Fast IrDA controller (FIrDA)
The fast IrDA controller is a programmable infrared controller that acts as an interface to an
off-chip infrared transceiver. This controller is able to perform the modulation and the
demodulation of the infrared signals and the wrapping of the IrDA link access protocol
(IrLAP) frames.
Doc ID 16324 Rev 2
17/83
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