SPEAr300
Table 10. Available peripherals in each configuration mode
Pin description
GPIOs
1
16-bit
NAND
4
2
16-bit
NOR
4
3
16-bit
NAND
1
4
81
1
18 6 12
6
18 6 12
6
18
28 28
22
8 8 9*9 62 38 8 12 4 14
5
4111
2 8 9*9 42 38
4
14
6
81
1
8 8 9*9 58 38 8 8 4 14
7
8
8-bit
NOR
8-bit
9 NAND
/NOR
10
4111
8
2 8 9*9 42 38
4
14
84
44 24 8 8 4 14
81
41
1
44
42 24 8 8 2 14
1 8-bit 2 8 9*9 36 32
4
10
11
1 1 1 14-bit 2 8 7*5 26 26
10
12
1
1 14-bit 2 8 7*5 26 26
10
13
4 1 1 1 8-bit 2 8 9*9 32 28
4
6
TDM interfacing using GPIOs
In some configuration modes where less than 8 TDM devices are indicated in Table 10,
additional TDM devices can be supported by using GPIO pins. The TDM needs a dedicated
interrupt line, an SPI and an independent frame sync signal to interface each device. When
enough SPI chip selects signals are not available (SPI_I2C signals), the chip select can be
performed by a GPIO. In this case the number of possible TDM devices supported is:
Modes 5, 7, 8 and 9: up to 8 devices
Modes 3 and 10: up to 6 devices
Modes 11 and 12: up to 4 devices
Doc ID 16324 Rev 2
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