SPEAr300
Pin description
Notes/legend for Table 11:
GPIO (General purpose I/O):
basGPIO: Base GPIOs in the basic subsystem (enabled as alternate functions)
G10 and G8: GPIOs in the RAS subsystem
GPIOx: GPIOs in the independent GPIO block in the RAS subsystem
TDM_ : TDM interface signals
SD_ : SDIO interface
IT pins: interrupts
Table cells filled with ‘0’ or ‘1’ are unused and unless otherwise configured as Alternate
function or GPIO, the corresponding pin is held at low or high level respectively by the
internal logic.
Table cells filled with ‘Reserved’ denote pins that must be left unconnected.
Table 12.
Table shading
Shading
FSMC
Keyboard
CLCD
CAMERA
UART
Ethernet MAC
SDIO/MMC
GPT
IrDa
SSP
I2C
Pin group
FSMC pins: NAND or NOR Flash
Keyboard pins ROWs are outputs, COLs are inputs
Color LCD controller pins
Camera pins
UART pins
MII/SMII Ethernet Mac pins
SD card controller pins
Timer pins
IrDa pins
SSP pins
I2C pins
3.4
PL_GPIO pin sharing for debug modes
In some cases the PL_GPIO pins may be used in different ways for debugging purposes.
There are three different cases (see also Table 13):
1. Case 1 - All the PL_GPIO get values from Boundary scan registers during Ex-test
instruction of JTAG . Typically this configuration is used to verify correctness of the
soldering process during the production flow .
2. Case 2 - All the PL_GPIO maintain their original meaning but the JTAG Interface is
connected to the processor. This configuration is useful during the development phase
but offers only "static" debug.
3. Case 3 - Some PL_GPIO, as shown inTable 13: Ball sharing during debug, are used to
connect the ETM9 lines to an external box. This configuration is typically used only
during the development phase. It offers a very powerful debug capability. When the
processor reaches a breakpoint it is possible, by analyzing the trace buffer, to
understand the reason why the processor has reached the break.
Doc ID 16324 Rev 2
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