SPEAR300-2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
SPEAR300-2
STMicroelectronics
'SPEAR300-2' PDF : 83 Pages View PDF
Table 11. PL_GPIO multiplexing scheme (continued)
PL_GPIO_# /
ball number
1
2
3
Configuration mode (enabled by RAS register 2)
Alternate
function
(enabled
4
5
6
7
8
9
10
11
12
13
by RAS
register 1)
PL_GPIO_73/A17
0
PL_GPIO_72/B16
0
PL_GPIO_71/D14
0
PL_GPIO_70/C15
0
PL_GPIO_69/A16
0
PL_GPIO_68/B15
0
PL_GPIO_67/C14
0
PL_GPIO_66/E13
0
PL_GPIO_65/B14
0
PL_GPIO_64/D13
0
PL_GPIO_63/C13
0
PL_GPIO_62/A15
0
PL_GPIO_61/E12
0
PL_GPIO_60/A14
0
PL_GPIO_59/B13
0
PL_GPIO_58/D12
CL
PL_GPIO_57/E11
AL
PL_GPIO_56/C12
/W
PL_GPIO_55/A13
/R
PL_GPIO_54/E10
0
PL_GPIO_53/D11
0
PL_GPIO_52/B12
0
A7
CLD7
G8_7 (out)
CLD7
0
CLD7
A7
A7
Reserved CLD7 Reserved CLD7
A8
CLD8
IT0
CLD8
IT0
CLD8
IT0
IT0
Reserved CLD8 Reserved CLD8
A9
CLD9
IT1
CLD9
IT1
CLD9
IT1
IT1
Reserved CLD9 Reserved CLD9
A10
CLD10
IT2
CLD10
IT2
CLD10
IT2
IT2
Reserved CLD10 Reserved CLD10
A11
CLD11
IT3
CLD11
IT3
CLD11
IT3
IT3
Reserved CLD11 Reserved CLD11
A12
CLD12
IT4
CLD12
IT4
CLD12
IT4
IT4
Reserved CLD12 Reserved CLD12
A13
CLD13
IT5
CLD13
IT5
CLD13
IT5
IT5
Reserved CLD13 Reserved CLD13
A14
CLD14
IT6
CLD14
IT6
CLD14
IT6
IT6
Reserved CLD14 Reserved CLD14
A15
CLD15
IT7
CLD15
IT7
CLD15
IT7
IT7
Reserved CLD15 Reserved CLD15
A16
CLD16
SPI_I2C4
CLD16 SPI_I2C4 CLD16 SPI_I2C4 SPI_I2C4 Reserved CLD16 Reserved CLD16
A17
CLD17
SPI_I2C5
CLD17 SPI_I2C5 CLD17 SPI_I2C5 SPI_I2C5 Reserved CLD17 Reserved CLD17
A18
CLD18
SPI_I2C6
CLD18 SPI_I2C6 CLD18 SPI_I2C6 SPI_I2C6 Reserved CLD18 Reserved CLD18
A19
CLD19
SPI_I2C7
CLD19
SPI_I2C7
CLD19
SPI_I2C7
/DOUT
SPI_I2C7
/DOUT
Reserved
CLD19
Reserved
CLD19
A20
CLD20
TDM_
SYNC4
CLD20
TDM_
SYNC4
CLD20
TDM_
SYNC4
TDM_
SYNC4
Reserved
CLD20
Reserved
CLD20
A21
CLD21
TDM_
SYNC5
CLD21
TDM_
SYNC5
CLD21
TDM_
SYNC5
TDM_
SYNC5
Reserved
CLD21
Reserved
CLD21
A22
CL
TDM_
SYNC6
CLD22
TDM_
SYNC6
CLD22
TDM_
SYNC6
CL
Reserved CLD22 Reserved CLD22
A23
AL
TDM_
SYNC7
CLD23
TDM_
SYNC7
CLD23
TDM_
SYNC7
AL
Reserved CLD23 Reserved CLD23
/W
/W
ROW7
ROW7
ROW7
ROW7
/W
/W
ROW7 VSYNC_1 VSYNC_1 ROW7
/G
/R
ROW8
ROW8
ROW8
ROW8
/R
/R
ROW8 HSYNC_1 HSYNC_1 ROW8
0
CLAC
G10_9
CLAC
G10_9
CLAC
G10_9 G10_9
G10_9
CLAC
G10_9
CLAC
0
CLCP
G10_8
CLCP
G10_8
CLCP
G10_8 G10_8
G10_8
CLCP
G10_8
CLCP
0
CLFP
G10_7
CLFP
G10_7
CLFP
G10_7 G10_7
G10_7
CLFP
G10_7
CLFP
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