SPEAR300-2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
SPEAR300-2
STMicroelectronics
'SPEAR300-2' PDF : 83 Pages View PDF
Timing requirements
SPEAr300
6.2.1
MHz), setting BCD bit to '1', and the second one with the clock passing through a clock
divider (83 MHz), setting BCD bit to '0'.
CLCD timing characteristics direct clock
Figure 13. CLCD waveform with CLCP direct
CLCP
Tclock
Tmax
Tmin
CLD[23:0],CLAC,CLLE,CLLP,
CLFP ,CLPOWER
Tstabl e
Tf
Tr
Figure 14. CLCD block diagram with CLCP direct
t1
CLCDCLK
D Q SET
Q CL R
t3
CLD[23:0],CLAC,CLLE,
CLLP,CLFP,CLPOWER
t2
CLCP
Table 29. CLCD timings with CLCP direct
Parameter
Value
tCLOCK direct max (tCLOCK )
tCLOCK direct max rise (tr)
tCLOCK direct max (tf)
tmin
tmax
tSTABLE
6 ns
0.81 ns
0.87 ns
-0.04 ns
3.62 ns
2.34 ns
Frequency
166 MHz
Note: 1 tSTABLE = tCLOCK direct max - (tmax + tmin)
2 For tmax the maximum value is taken from the worst case and best case, while for tmin the
minimum value is taken from the worst case and best case.
3 CLCP should be delayed by {tmax + [tCLOCK direct max - (tmax + tmin)]/2} = 4.7915 ns
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Doc ID 16324 Rev 2
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