ST18-AU1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18-AU1' PDF : 87 Pages View PDF
ST18-AU1
PCMCR: Data in control register
All bits are cleared on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - Mute play mute PCM Mode - Justi- De- WS_p CLK_ WS
PC-
_en
_ord
fied layed ol pol
MEN
Bit
PCMEN
WS
CLK_pol
WS_pol
Delayed
Justified
Mode
PCM_ord
Function
PCM output enable
0
disable
1
enable
Output word size
bit 1 bit 0
0
0
0
1
1
0
1
1
word size
16 bit
18 bit
20 bit
24 bit
Clock pol
0
1
data and WS change on SCLKPCM falling edge
data and WS change on SCLKPCM rising edge
Word size pol
0
Left data word = WS low, Right data word = WS high
1
Left data word = WS high, Right data word = WS low
Delayed
0
first bit of data occurs on transition of WS
1
first bit of data occurs with 1 SCLKPCM cycle delay relative to
transition of WS. (I2S compatible).
Note: valid only for start justified mode, see bit 6.
If number of SCLKPCM cycles between WS transitions is > N (=Word size)
0
start justified: N bits read, starting from first bit:
just after WS transition if Delayed =’0’
with 1 clk cycle delay after WS transition if Delayed =’1’
1
end justified, end bit in last bit received:
just before WS transition if Delayed =’0’
just after WS transition if Delayed =’1’
Mode
0
1
2 channels
6 channels
In 16-bit word-size,
0
MSB sent first
1
LSB sent first
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