ST18-AU1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18-AU1' PDF : 87 Pages View PDF
ST18-AU1
Bit
CPL
ES
SPL1
SPL2
SPL3
SPL4
Function
Current priority level (-1, 0, 1, 2 or 3) (default is 011)
Empty stack flag
0: stack is used
1: stack is not used (default)
3-bit 1st stacked priority level
3-bit 2nd stacked priority level
3-bit 3rd stacked priority level
3-bit 4th stacked priority level
The current priority levels available are shown below.
Priority level
-1
0
1
2
3
Reserved
Coding
111
000
001
010
011
100 - 110
Acceptable IT level priority
0,1,2,3
1,2,3
2,3
3
One interrupt request is acknowledged whenever its priority level (coded in the IPR register)
is higher than the current priority level. In this case, the current priority level becomes the
interrupt priority level and the previous current priority level is pushed onto the stack and
displayed as stack priority level (SPL)1.
The process is repeated over a range of four interrupt requests and the four previous current
stack priority levels are displayed on SPL1, SPL2, SPL3 and SPL4. If less than four interrupts
are pushed onto the stack, the unused SPL words are set to ‘000’. At the end of the interrupt
routine, the priority levels are popped from the stack.
The empty stack (ES) flag is used to indicate whether the stack is used or not. The ISP word
of the ISP register indicates the depth of the stack (see below).
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