ST18-AU1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18-AU1' PDF : 87 Pages View PDF
Figure 8.2
ICR and ISPR Operation
INTERRUPT LEVEL 2
PROGRAM
IT2
PROGRAM IT2
IT3
ST18-AU1
INTERRUPT LEVEL 3
PROGRAM IT3
ICR
SPL4 SPL3 SPL2 SPL1 ES CPL
X X X X 1 -1
ISPR
ISP
0
SPL4 SPL3 SPL2 SPL1 ES CPL
X X X -1 0 2
ISP
1
SPL4 SPL3 SPL2 SPL1 ES CPL
X X -1 2 0 3
ISP
2
VR02020D
IMR: Interrupt mask/sensitivity register
(Address = 0029, Reset = 5555h, Read/Write))
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IS7 IM7 IS6 IM6 IS5 IM5 IS4 IM4 IS3 IM3 IS2 IM2 IS1 IM1 IS0 IM0
Bit
Function
IM
Interrupt mask
0: Interrupt is not masked
1: Interrupt is masked (default)
IS
Sensitivity
0: ITRQ is active on a low level (default)
1: ITRQ is active on a falling edge
Each interrupt input ITRQ0-7 can be masked individually when the corresponding IM0-7 bit is
set. In this case any activity on the ITRQ0-7 pin is ignored. All IM bits are set during DSP reset.
ITRQ0-7 is active either on a low level when IS0-7 is low (by default on reset) or on a falling
edge when IS0-7 is high.
When ITRQ0-7 is active on a low level, it must stay low until the ITACK falling edge is sampled.
Note, edge sensitive mode of operation must be set for all internal interrupt sources.
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