ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
Figure 8.1 D950Core interrupt controller
ST18-AU1
AS-DSP
16
YD
YA
16
D950Core
IT
ITACK
EOI
YWR
YRD
INCYCLE
IT
ITACK
EOI INTERRUPT
YWR CONTROLLER
YRD PERIPHERAL
CLK
ITRQ0
ITRQ1
ITRQ2
ITRQ3
ITRQ4
ITRQ5
ITRQ6
ITRQ7
RESET
VR02020C
8.1 Interrupt controller registers
The interrupt controller interface is controlled by status and control registers mapped into the
Y-memory space. Status registers are not write-protected.
IVO0-7: Interrupt vector0-7 address registers
The IVO0-7 registers contain the first address of the interrupt routine and are associated with
the respective interrupt input ITRQ, see Table 8.1. The register content of the interrupt under
service is provided on the YD bus during the cycle following the ITACK falling edge.
(Address = 0020-0027, No reset value, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVi15 IVi14 IVi13 IVi12 IVi11 IVi10 IVi9 IVi8 IVi7 IVi6 IVi5 IVi4 IVi3 IVi2 IVi1 IVi0
ICR: Interrupt control register
The ICR register displays the current priority level and up to four stacked priority levels.
(Address = 0028, Reset = 000Bh, Read/Write))
15 14 13 12 11 10 9 8 7
SPL4 (2:0)
SPL3 (2:0)
SPL2 (2:0)
65 4
SPL1 (2:0)
32 1 0
ES
CPL (2:0)
35/87
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