ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
ST18-AU1
An interrupt pending (IPE) bit is associated with each interrupt input. IPE is set when the
interrupt request is recorded and is reset when the interrupt request is acknowledged (ITACK
falling edge).
When the user does not want to acknowledge any of the pending interrupt requests, the IPE
flag of the CCR register must first be reset and then the ISR register set to “0000”.
When only some pending interrupt requests need to be acknowledged, the IPE bits of the other
interrupt inputs must be reset.
When the IPE bit is set by a direct register write an interrupt request will be generated
irrespective of the state of the ITRQ pin.
When the mask (IM) bit is set, the corresponding IPE bit is reset.
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