ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
ST18-AU1
9 DMA CONTROLLER
The DMA controller manages data transfer between memories and external peripherals and
has the following features:
• four independent DMA channels
• transfers on X / Y / I spaces (simultaneous transfers on X and Y spaces)
• cycle stealing operation:
• 3 cycles for a single data transfer (+1 cycle for transfers on I space)
• (n+2) cycles for an n-data block transfer (+1 cycle for transfers on I space)
• each channel has:
• 1 signal: interrupt request (ITR)
• 4x16 bit registers for block transfer facilities
• fixed priority between the four channels (highest for channel 0, lowest for
channel 3)
9.1 DMA operation
The four channels of D950 DMAC are used for:
• DMA3: transfer data from input FIFO to input buffer (Y space).
As single words are transferred, it must be programmed edge sensitive.
• transfer data from output buffer to PCM output (X space).
• DMA0 in 2-channel output mode
• DMA0, DMA1 and DMA2 in 6-channel output mode
they must be programmed level sensitive.
• DMA1: transfer data from input buffer or output buffer to SPDIF interface.
This channel will be programmed for transfer with X or Y memory according to
the mode of operation of the SPDIF transmitter. It must be programmed level
sensitive.
(not compatible with 6-channel output mode.)
• DMA2: transfer data from DATA Input1 to Y memory.
As single words are transferred, it must be programmed edge sensitive.
(not compatible with 6-channel output mode.)
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