ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
ST40RA166
5 Clock generation
4.8.7 PCI.PERF register definition.
PCI.PERF
PCI.PERF modifies the function of the PCI.
[3:0] DLY_PERRSAMPLE
Parity error delay
Number of app_clock cycles after end of PCI that access master
should wait to see if there is a parity error
4 ENB_WRITEPOST
Enable write posting in master
5 ENB_STBYBYPASS
Enable standby bypass
[31:6] Reserved
0x0080
RW
RW
RW
5 Clock generation
The ST40 clock architecture has been organized to maintain compatibility across the ST40 family
and allow additional flexibility to increase system performance where required. It includes a more
diverse range of peripherals and provides low power use.
5.1 Clock domains and sources
Figure 4 shows possible clock domains for ST40RA166 clocks. The ST40RA166 implementation
includes two CLOCKGEN macros, which supply up to three independent clock domains across the
chip
Each PLL may be independently programmed to produce a clock at a specific frequency which is
used to derive a series of related clocks which may be used by the system.
The clock domains mapping is shown in Table 12. The architecture of the ST40RA166 CLOCKGEN
subsystem consists of two standard (ST40 family) CLOCKGEN units (CLOCKGENA and
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