ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
ST40RA166
5 Clock generation
Subsystem
Clock domain
Target frequencies
(MHz)
Sourcea
CPU core
SuperHyway
Peripherals
PCI bus clock
CPU_CLK
STBUS_CLK
PER_CLK
(CPU core PCK)
PCI_BUS_CLK
PCI subsystem
PCI_SS_CLK
Local memory
interface (LMI)
EMI subsystem
LMI_CLK
EMI_CLK
200 166 150 133 CLOCKGEN_A11
-
111 100 88 CLOCKGEN_A12
100 83 75 67
-
55 50 44 CLOCKGEN_A13
50 42 38 33
33
CLOCKGEN_A21
66
CLOCKGEN_A22
25.14
CLOCKGEN_A23
Disabled
CLOCKGEN_A24
-
111 100 88 CLOCKGEN_A12
100 83 75 67
-
55 50 44 CLOCKGEN_A13
50 42 38 33
133 111 100 88 CLOCKGEN_A14
Reserved
CLOCKGEN_B11
50 to 100 MHz
CLOCKGEN_B12
-
111 100 88 CLOCKGEN_A12
100 83 75 67 CLOCKGEN_A14
Table 12: Clock domains
a. Clock naming: CLOCKGEN_[CLOCKGEN label][PLL number][clock number]
Ratio
1
2/3
1/2
1/3
1/4
1/16
1/8
1/21
-
2/3
1/2
1/3
1/4
2/3
1
1
2/3
1/2
The sources for PCI_SS_CLK and EMI_SS_CLK, can be set using the PCI_SEL and EMI_SEL bits in the
CLOCKGENB.CLK_SELCR register. See Section 5.6.1: CLOCKGENB.CLK_SELCR register on
page 36.
If CLOCKGEN_A13 is used as PCI_SS_CLK source then the memory bridges 6 and 7 must be
enabled. If CLOCKGEN_A12 is used, then the bridges may be placed in bypass mode. This is the
recommended mode of operation.
If either CLOCKGEN_B12 or CLOCKGEN_A14 are used as the EMI_CLK, the memory bridges 1, 2
and 3 must be enabled. If CLOCKGEN_A12 is used, then the bridges may be placed in bypass.
This is the recommended mode of operation.
See Chapter 4.7: Memory bridge control on page 19.
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