ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
5 Clock generation
ST40RA166
CLOCKGENB) and a CLOCKCON block. Figure 5 shows the architecture of the ST40RA166
CLOCKGEN subsystem.
STBUS_CLK
(X_BCK)
SuperHyway
CPU_CLK (X_ICK)
PER_CLK (X_PCK)
SHc-4orCePU
SH-4 core
peripherals
27 MHz
XTAL
CLOCKGEN
subsystem
STBUS_CLK
LMI_CLK
EMI_SS_CLK
PCI_SS_CLK
PCI_BUS_CLK
LMI LMI int
DLL
CLK SDRAM
or DDR
memory
EMI
subsystem
CLK Flash.
MPX bus,
SDRAM
PCI
subsystem
PCI int.
CLK
PCI
bus
See CLOCKGENA.PLL1 clock domains
See CLOCKGENA.PLL2 clock domains
See CLOCKGENB.PLL1 clock domains
Figure 4: ST40RA166 clock domains
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