ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
ST40RA166
5 Clock generation
5.2 Recommended operating modes
Mode for
CLOCKGENA and
CLOCKGENB
PLL
frequency
(MHz)
ST40RA166 clock domain frequencies (MHz)
PLLA
(mode)
PLLB
(mode)
PLLA
PLLB
CPU_
CLK
STBUS_
CLK
PER_
CLK
LMI_
CLK
EMI_SS_
CLK
PCI_SS_
CLK
Recommended reset configuration
0
-
200
-
100
50
25
50
50
50
Alternate reset configuration
1
-
266
-
133
88
44
88
88
88
2
-
300
-
150
100
50
100
100
100
3
-
332
-
166
111
66
111
111
111
Recommended operating modes
2
-
300
-
150
100
100
100
100
100
3
-
332
-
166
83
83
83
83
83
Low power configuration with clocks enabled (programmable after reset)
A6
-
27
-
13.5
6.75
6.75
6.75
6.75
6.75
bypass
Table 13: Supported operating frequencies
5.3 Clocks and registers at start up
Reset
mode
Reset CLOCKGENA
mode
.PLL1CR1
MODE[2:0] reset value
CLOCKGENA
core
frequency
(PLL1)
fPLL/2
CLK1
CPU_
CLK
CLK2
STBUS_
CLK
CLK3
PER_
CLK
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
0x7939 8612
200 MHz
100
1
1/2
1/4
0x7939 B112
266 MHz
133
1
2/3
1/3
0x7938 6412
300 MHz
150
1
2/3
1/3
0x7938 7B14
332 MHz
166
1
2/3
1/3
0x7938 8612
400 MHz
200
1
1/2
1/4
0x7938 A712
500 MHz
250
1
1/2
1/4
0x0938 0000
0 MHz
0
1
1/2
1/2
0x0939 8612
200 MHz
100
1/2
1/4
1/4
Table 14: CLOCKGENA PLL1 reset values
CLK4
LMI_
CLK
1/2
2/3
2/3
2/3
1/2
1/2
1/2
1/4
32/88
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