ST40RA166 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST40RA166

32-bit Embedded SuperH Device

STMicroelectronics 

Prev 31 32 33 34 35 36 37 38 39 40 Next

5 Clock generation

ST40RA166

5.3.1 CLOCKGENA_2x PCI (PCI_DIV_BYPASS = 0)

Reset mode

MODE[4:3]

Reset value

PLL2 frequency

00

0x7938 B012

528 MHz

01

0x7938 B012

528 MHz

10

0x7938 B012

528 MHz

11

0x0938 B012

0 MHz

Table 15: CLOCKGENA PLL2 reset values (PCI_DIV_BYPASS = 0)

5.3.2 Division ratios on CLOCKGENA_2x

Mode

MODE[4:3]

Divide ratio selected PCI_BUS_CLK freq.

00

8

66 MHz

01

16

33 MHz

10

21

25.14 MHz

11

-

0 MHz

Table 16: CLOCKGENA_PLL2 PCI reset division ratios.

5.4 Setting clock frequencies

Table 17 shows valid FRQCR ratios and the associated clock frequencies for derived clocks.

CLOCKGENA.FRQCR and

CLOCKGENB.FRQCR

ST40RA166 codified ratios

Clock ratios

Lower 9 bit

0x000

0x002

0x004

0x008

0x00A

0x00C

0x011

0x013

0x01A

0x01C

0x023

Available

on start up

CPU_

CLK

BUS_

CLK

PER_

CLK

CPU_

CLK

MODE6

MODE[4:5]

MODE[2:3]

MODE0

MODE1

1/2

1

1

1

1/4

1

1/8

1

1

1/2

1

1/2

1/4

1

1/2

1/8

1

2/3

1/6

1

2/3

1/3

1

1

1/2

1/4

1

1/8

1

1

2/3

1/3

1

Table 17: Valid FRQCR values and their ratios

BUS_

CLK

1

1

1

1/2

1/2

1/2

2/3

2/3

1/2

1/2

2/3

PER_

CLK

1/2

1/4

1/8

1/2

1/4

1/8

1/6

1/3

1/4

1/8

1/3

33/88

Share Link: