5 Clock generation
ST40RA166
5.6.6 CLOCKGENA.STBACKCR and CLOCKGENB.STBACKCR register
CLOCKGENA.STBACKCR
CLOCKGENB.STBACKCR
Current module power status
This register indicates the current module power status
[0:7] ACK[0:7]
[8:31] Reserved
Power down status for module [n]
Indicates the current power down status of the
module [n]
Bit [n]: 0 Module [n] operating normally
Bit [n]: 1 Module [n] powered down
Reset state: 0
0: No action
1: Undefined
Reset state: Undefined
0x0030
RO
Table 18 defines the mapping of modules to bits in the STBREQ and STBACK registers.
Bit number
CLOCKGENA
mapping
CLOCKGENB
mapping
0
EMI
Reserved
1
LMI
Reserved
2
DMAC
Reserved
3
PCI
Reserved
4
PIO
Reserved
5
Reserved
Reserved
6
Reserved
PCI bus
7
Reserved
Reserved
Table 18: STBREQ and STBACK mapping for modules
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