ST6369 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6369' PDF : 71 Pages View PDF
ST6369
ST6369 CORE (Continued)
Stack
The ST6369 Core includes true LIFO hardware
stack that eliminates the need for a stack pointer.
The stack consists of six separate 12-bit RAM loca-
tions that do not belong to the data space RAM
area. When a subroutine call (or interrupt request)
occurs, the contents of each level is shifted into the
next level while the content of the PC is shifted into
the first level (the value of the sixth level will be
lost). When subroutine or interrupt return occurs
(RET or RETI instructions), the first level register is
shifted back into the PC and the value of each level
is shifted back into the previous level. These two
operating modes are described in Figure 5. Since
the accumulator, as all other data space registers,
is not stored in this stack the handling of this regis-
ters shall be performed inside the subroutine. The
stack pointer will remain in its deepest position, if
more than 6 calls or interrupts are executed, so
that the last return address will be lost. It will also
remain in its highest position if the stack is empty
and a RET or RETI is executed. In this case the
next instruction will be executed.
Memory Registers
The PRPR can be addressed like a RAM location
in the Data Space at the CAH address; neverthe-
less it is a write-only register that can not be ac-
cessed with single-bit operations. This register is
used to select the 2-Kbyte ROM bank of the Pro-
gram Space that will be addressed. The number of
the page has to be loaded in the PRPR. The PRPR
is not cleared during the MCU initialization and
should therefore be defined before jumping out of
the static page. Refer to the Program Space de-
scription for additional information concerning the
use of this register. The PRPR is not modified
when an interrupt or a subroutine occurs.
Figure 6. Program ROM Page Register
PRPR
Program ROM Page Register
(CAH, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
The DRBR can be addressed like a RAM location
in the Data Space at the E8H address, neverthe-
less it is write-only register that can not be ac-
cessed with single-bit operations. This register is
used to select the desired 64-byte RAM/EEPROM
bank of the Data Space. The number of the bank
has to be loaded in the DRBR and the instruction
has to point to the selected location as it was in the
0 bank (from 00H address to 3FH address). This
register is undefined after Reset. Refer to the Data
Space description for additional information. The
DRBR register is not modified when a interrupt or
a subroutine occurs.
Figure 7. Data RAM Bank Register
DRBR
Data RAM Bank Register
(E8H, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
The DRWR register can be addressedlike a RAM lo-
cation in the Data Space at the C9H address, never-
theless it is write-only register that can not be
accessed with single-bit operations. This register is
used to move up and down the 64-byte read-only
data window (from the 40H address to 7FH address
of the Data Space) along the ROM of the MCU by
step of 64 bytes. The effective address of the byte to
be read as a data in the ROM is obtainedby the con-
catenationof the 6 less significant bits of the address
given in the instruction (as less significant bits) and
the content of the DRWR (as most significant
bits). Refer to the Data Space description for addi-
tional information.
Figure 8. Data ROM Window Register
DRWR
Data ROM Window Register
(C9H, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
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