ST6369 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6369' PDF : 71 Pages View PDF
ST6369
INTERRUPT (Continued)
Table 6. Interrupt Vectors/Sources
Relationships
Interrupt Source
Associated
Vector
Vector Address
PC6/IRIN
Pin (1)
Interrupt
Vector # 0 (NMI)
0FFCH-0FFDH
Timer 2
Interrupt
Vector # 1
0FF6H-0FF7H
Vsync
Interrupt
Vector # 2
0FF4H-0FF5H
Timer 1
Interrupt
Vector # 3
0FF2H-0FF3H
PC4/PWRIN
Interrupt
Vector # 4
0FF0H-0FF1H
Note: 1. This pin is associated with the NMI Interrupt Vector
The interrupt vector associated with the non-mask-
able interrupt source is named interrupt vector #0.
It is located at the (FFCH,FFDH) addresses in the
Program Space. This vector is associated with the
PC6/IRIN pin.
The interrupt vectors located at addresses
(FF6H,FF7H), (FF4H,FF5H), (FF2H,FF3H),
(FF0H,FF1H) are named interrupt vectors #1, #2,
#3 and #4 respectively. These vectors are associ-
ated with TIMER 2 (#1), VSYNC (#2), TIMER 1
(#3) and PC4(PWRIN) (#4).
Interrupt Priority
The non-maskable interrupt request has the high-
est priority and can interrupt any other interrupt
routines at any time, nevertheless the other inter-
rupts cannot interrupt each other. If more than one
interrupt request is pending, they are processed by
the ST6369 Core according to their priority level:
vector #1 has the higher priority while vector #4 the
lower. The priority of each interrupt source is hard-
ware fixed.
Interrupt Option Register
The Interrupt Option Register (IOR register, loca-
tion C8H) is used to enable/disable the individual
interrupt sources and to select the operating mode
of the external interrupt inputs. This register can be
addressed in the Data Space as RAM location at
the C8H address, nevertheless it is write-only reg-
ister that can not be accessed with single-bit op-
erations. The operating modes of the external
interrupt inputs associated to interrupt vectors #1
and #2 are selected through bits 4 and 5 of the IOR
register.
Figure 18. Interrupt Option Register
IOR
Interr upt Option Register
(C8H, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Unuse d
GEN = Global Enab le Bit
ES2 = Edge Selection Bit
EL1 = Edge Level Selection Bit
Unuse d
D7. Not used.
EL1. This is the Edge/Level selection bit of inter-
rupt #1. When set to one, the interrupt is generated
on low level of the related signal; when cleared to
zero, the interrupt is generated on falling edge. The
bit is cleared to zero after reset.
ES2. This is the edge selection bit on interrupt #2.
This bit is used on the ST6369 devices with on-chip
OSD generator for VSYNC detection.
GEN. This is the global enable bit. When set to one all
interrupts are globally enabled; when this bit is cleared
to zero all interrupts are disabled (excluding NMI).
D3 - D0. These bits are not used.
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