ST6369 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6369' PDF : 71 Pages View PDF
ST6369
MEMORY SPACES (Continued)
ting PE without programming the EEPROM. After
the ROW address latching the Core can “see” just
one EEPROM row (the selected one) and any at-
tempt to write or read other rows will produce er-
rors. Do not read the EEPROM while PE is set.
As soon as PE bit is set, the 8 volatile ROW latches
are cleared. From this moment the user can load
data in the whole ROW or just in a subset. PS set-
ting will modify the EEPROM registers correspond-
ing to the ROW latches accessed after PE. For
example, if the software sets PE and accesses
EEPROM in writing at addresses 18H,1AH,1BHand
then sets PS, thesethree registers will be modified at
the same time; the remaining bytes will have no par-
ticular content. Note that PE is internally reset at the
end of the programming procedure. This implies that
the user must set PE bit between two parallel pro-
gramming procedures. Anyway the user can set and
then reset PE without performing any EEPROMpro-
gramming. PS is a set only bit and is internally reset
at the end of the programming procedure. Note that
if the user tries to set PS while PE is not set there will
not be any programming procedure and the PS bit
will be unaffected. Consequently PS bit can not be
set if EN is low. PS can be affected by the user set if,
and only if, EN and PE bits are also set to one.
INTERRUPT
The ST6369 Core can manage 4 different mask-
able interrupt sources, plus one non-maskable in-
terrupt source (top priority level interrupt). Each
source is associated with a particular interrupt vec-
tor that contains a Jump instruction to the related
interrupt service routine. Each vector is located in
the Program Space at a particular address (see
Table 6). When a source provides an interrupt re-
quest, and the request processing is also enabled
by the ST6369 Core, then the PC register isloaded
with the address of the interrupt vector (i.e. of the
Jump instruction). Finally, the PC is loaded with the
address of the Jump instruction and the interrupt
routine is processed.
The relationship between vector and source and
the associated priority is hardware fixed for the dif-
ferent ST638x devices. For some interrupt sources
it is also possible to select by software the kind of
event that will generate the interrupt.
All interrupts can be disabled by writing to the GEN
bit (global interrupt enable) of the interrupt option
register (address C8H). After a reset, ST6369 is in
non maskable interrupt mode, so no interrupts will
be accepted and NMI flags will be used, until a
RETI instruction is executed. If an interrupt is exe-
cuted, one special cycle is made by the core, dur-
ing that the PC is set to the related interrupt vector
address. A jump instruction at this address has to
redirect program execution to the beginning of the
related interrupt routine. The interrupt detecting cy-
cle, also resets the related interrupt flag (not avail-
able to the user), so that another interrupt can be
stored for this current vector, while its driver is un-
der execution.
If additional interrupts arrive from the same source,
they will be lost. NMI can interrupt other interrupt
routines at any time, while other interrupts cannot
interrupt each other. If more than one interrupt is
waiting for service, they are executed according to
their priority. The lower the number, the higher the
priority. Priority is, therefore, fixed. Interrupts are
checked during the last cycle of an instruction
(RETI included). Level sensitive interrupts have to
be valid during this period.
Table 6 details the different interrupt vec-
tors/sources relationships.
Interrupt Vectors/Sources
The ST6369 Core includes 5 different interrupt
vectors in order to branch to 5 different interrupt
routines. The interrupt vectors are located in the
fixed (or static) page of the Program Space.
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