ST70135 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70135' PDF : 29 Pages View PDF
Figure 11 : Generic Processor Interface Read Timing Cycle
ALE
CSB
AD(15-0)
RDB
READY
WRB
Talew Tale2Z
Tavs
Tavh
Trd2cs
Tale2cs
Tcsrd
Twr2d
Tdvh
Twdvd
Twrw
Tmclk
Tcsrs
Tcsre
Trdy2dr
ST70135A
Generic processor interface Cycle Timing
All AC characteristics are indicated for a 100pF capacitive load.
Symbol
tr & tf
Talew
Tavs
Tavh
Tale2cs
Tale2Z
Tcs2rdy
Tcsre
Tcs2wr
Twr2d
Trdy2wr
Tdvs
Tdvh
Twr2cs
Tcs2rd
Trdy2rd
Trd2cs
Tmclk
Parameters
Rise & Fall time (10% to 90%)
ALE pulse width
Address Valid setup time
Address Valid Hold time
ALE to CSB
ALE to high Z state of address bus
CSB to RDYB asserted
Access Time
CSB to WRB
WRB to data
RDYB to WRB
data setup time
data hold time
WRB to CSB
CSB to RDB
RDY to RDB
RDB to CSB
Master clock Timing
Minimum
12
10
10
0
0
0
10
1/2Tmclk
-10
0
0
-10
Typical
Maximum
3
50
60
900
15
Tmclk
Unit
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
15/29
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