ST70135 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70135' PDF : 29 Pages View PDF
ST70135A
Generic Processor Interface Pins and
Functional Description
Name
AD[0..15]
ALE
RDB
WRB
CSB
RDYB
INTB
Type
I/O
I
I
I
I
OZ
O
Function
Multiplexed address / data bus
Address Latch Enable
Read cycle indication
Write cycle indication
Chip Select
Bus cycle ready indication
Interrupt
Digital interface ATM or serial
Digital Interface for data to the loop
before modulation and from the loop after
demodulation.
This interface collects cells (from the cell based
function module) or a byte stream (from the
deframer).
Cells are stored in a fifo, 2 interfaces submodules
can extract data from the fifo. Byte streams are
dumped on the bitstream interface (with no fifo).
3 kinds of interface are allowed:
– Utopia Level 1
– Utopia Level 2
– Bitstream based on a proprietary exchange
The interface selection is programmed by writing
the Utopia PHY address register.
Only one interface can be enabled in a ST70135A
configuration.
Utopia Level 1 supports only one PHY device.
Utopia Level 2 supports multi-PHY devices (See
Utopia Level 2 specifications).
Each buffer provides storage for 8 ATM cells (both
directions for Fast and Interleaved channel).
The Utopia Level 2 supports point to multipoint
configurations by introducing an addressing
capability and by making distinction between
polling and selecting a device.
Figure 12 : Receive Interface
PHY
PHY
RECEIVE
RxREF*
RxCLAV
RxENB*
RxCLK
RxDATA 8
RxSOC
ATM
CELL
RECEIVE
Figure 13 : Transmit Interface
PHY
PHY
TRANSMIT
TxREF*
TxCLAV
TxENB*
TxCLK
TxDATA 8
TxSOC
ATM LAYER
CELL
TRANSMIT
Utopia Level 1 Interface
The ATM forum takes the ATM layer chip as a
reference. It defines the direction from ATM to
physical layer as the Transmit direction.
The direction from physical layer to ATM is the
Receive direction. Figures 12 & 13 show the
interconnection between ATM and PHY layer
devices, the optional signals are not supported
and not shown.
The Utopia interface transfers one byte in a single
clock cycle, as a result cells are transformed in 53
clock cycles.
Both transmit and receive are synchronized on
clocks generated by the ATM layer chip, and no
specific relationship between receive and transmit
clocks is required. In this mode, the ST70135A
can only support one data flow : either interleaved
or fast.
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