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ST70135 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
ST70135
ST-Microelectronics
STMicroelectronics ST-Microelectronics
'ST70135' PDF : 29 Pages View PDF
ST70135A
Figure 14 : Timing (Utopia 1 Receive Interface)
RxCLK
RxSOC
RxENB
RxDATA
X
H1
H2
P44
P45
P46
P47
P48
X
RxCLAV
Pin Description
Name Type
Meaning
Usage
Remark
RxClav
O Receive Cell available Signals to the ATM chip that the ST70135A Remains active for the entire
has a cell ready for transfer
cell transfer
RxEnb 1 I Receive Enable
Signals to the ST70135A that the ATM chip
will sample and accept data during next
clock cycle
RxData and RxSOC could be
tri-state when RxEnb* is
inactive (high). Active low
signal
RxClk
I Receive Byte Clock
Gives the timing signal for the transfer,
generated by ATM layer chip.
RxData
O Receive Data (8bits) ATM cell data, from ST70135A chip to ATM
chip, byte wide. Rx Data [7] is the MSB.
RxSOC O Receive Start Cell
Identifies the cell boundary on RxData
Indicate to the ATM layer
chip that RxData contains
the first valid byte of a cell.
RxRef 1 O Reference Clock
8 kHz clock transported over the network Active low signal
Note 1. Active low signal
When RxEnb is asserted, the ST70135A reads data from its internal fifo and presents it on RxData and
RxSOC on each low-to-high transition of RxClk, ie the ATM layer chip samples all RxData and RxSOC on
the rising edge of RxSOC on the rising edge of RxClk.
Pin Description
Name Type
Meaning
Usage
Remark
TxClav
TxEnb 1
TxClk
TxData
TxSOC
TxRef 1
O Transmit Cell
available
Signals to the ATM chip that the physical Remains active for the entire
layer chip is ready to accept a complete cell cell transfer
I Transmit Enable
Signals to the ST70135A that TxData and
TxSOC are valid
I Transmit Byte Clock Gives the timing signal for the transfer,
generated by ATM layer chip.
I Transmit Data (8bits) ATM cell data, from ATM layer chip to
ST70135A, byte wide. TxData [7] is the MSB.
I Transmit Start of Cell Identifies the cell boundary on TxData
TxData contains the first
valid byte of the cell.
I Reference Clock
8kHz clock from the ATM layer chip
Note 1. Active low signal
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