ST7FLUS5MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLUS5MCE
STMicroelectronics
'ST7FLUS5MCE' PDF : 124 Pages View PDF
Interrupts
ST7LUS5, ST7LU05, ST7LU09
7.4.2
SI register description
System integrity (SI) control/status register (SICSR)
SICSR
7
Reserved
-
6
5
CR[1:0]
R/W
4
3
Reserved
-
Reset value: 0000 0x00 (0xh)
2
1
0
LVDRF
Reserved
R/W
-
Table 19. SICSR register description
Bit Name
Function
t(s) 7
- Reserved, must be kept cleared.
RC oscillator frequency adjustment bits
uc 6:5 CR[1:0] These bits, as well as CR[9:2] bits in the RCCR register must be written
d immediately after reset to adjust the RC oscillator frequency and to obtain the
ro ) required accuracy. Refer to Section 6.1 on page 31.
P t(s 4:3 - Reserved, must be kept cleared
te c LVD reset flag
uct(s) - OObbssoolleete Produ 2 LVDRF
This bit indicates that the last reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared when read. See WDGRF flag description in
Section 10.1 for more details. When the LVD is disabled by option byte, the LVDRF
bit value is undefined.
Note: If the selected clock source is one of the two internal ones, and if VDD
remains below the selected LVD threshold during less than TAWU (33µs typ.), the
LVDRF flag cannot be set even if the device is reset by the LVD.
If the selected clock source is the external clock (CLKIN), the flag is never set if the
reset occurs during halt mode. In Run mode the flag is set only if fCLKIN is greater
than 10 MHz.
rod - 1:0 - Reserved, must be kept cleared
P t(s) Application notes
lete uc The LVDRF flag is not cleared when another reset type occurs (external or watchdog); the
d LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset
so ro can be detected by software while an external reset can not.
b P Table 20. System integrity register map and reset values
O leteAddress Register
(Hex.)
label
7
6
5
4
3
2
1
0
Obso 003Ah
SICSR
Reset value
0
CR1
0
CR0
0
0
LVDRF
0
x
0
0
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