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ST7FLUS5MCE View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'ST7FLUS5MCE' PDF : 124 Pages View PDF
ST7LUS5, ST7LU05, ST7LU09
Figure 19. Wait mode flowchart
WFI instruction
Power saving modes
Oscillator
On
Peripherals
On
CPU
Off
I bit
0
N
Reset
N
Y
Interrupt
OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucctt((ss)) 8.4
Y
Oscillator
On
Peripherals
Off
CPU
On
I bit
0
64 CPU clock cycle
delay
Oscillator
On
Peripherals
On
CPU
I bit
On
X (1)
Fetch reset vector
or service interrupt
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set
during the interrupt routine and cleared when the CC register is popped.
Active halt and halt modes
Active halt and halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the HALT instruction. The decision to enter either in active
halt or halt mode is given by the LTCSR/ATCSR register status as shown in the following
table:
Table 21. LTC/ATC low power mode selection
LTCSR TBIE bit ATCSR OVFIE bit ATCSRCK1 bit
0
x
x
0
0
x
ATCSRCK0 bit
0
x
Meaning
Active halt mode
disabled
0
1
1
1
1
x
x
x
Active halt mode
x
1
0
1
enabled
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