ST7FLUS5MCE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7FLUS5MCE

8-bit low cost, low pin-count MCU for automotive, with single voltage Flash memory, ADC, timers

STMicroelectronics 

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Power saving modes

ST7LUS5, ST7LU05, ST7LU09

The compatibility of watchdog operation with halt mode is configured by the “WDGHALT”

option bit of the option byte. The HALT instruction when executed while the watchdog

system is enabled, can generate a watchdog reset (see Section 14.1 on page 131 for more

details).

Figure 22. Halt timing overview

Run Halt

64 CPU cycle

delay

Run

Reset(1)

or

HALT

interrupt

instruction

) [active halt disabled]

Fetch

vector

OObbssoolleettee PPrroodduucctt((ss)) -- OObbssoolleettee PPrroodduucctt((ss) 1. A reset pulse of at least 42µs must be applied when exiting from halt mode.

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