ST7LUS5, ST7LU05, ST7LU09
8
Power saving modes
Power saving modes
8.1
Introduction
To give a large measure of flexibility to the application in terms of power consumption, five
main power saving modes are implemented in the ST7 (see Figure 21):
● Slow
● Wait (and slow wait)
● Active halt
● Auto wake-up from halt (AWUFH)
● Halt
t(s) After a reset the normal operating mode is selected by default (run mode). This mode drives
the device (CPU and embedded peripherals) by means of a master clock which is based on
c the main oscillator frequency (fOSC).
du From run mode, the different power saving modes may be selected by setting the relevant
ro ) register bits or by calling the specific ST7 software instruction whose action depends on the
P t(s oscillator status.
lete uc Figure 17. Power saving mode transitions
so rod High
b P Run
) - O lete Slow
ct(s bso Wait
rodu ) - O Slow wait
te P ct(s Active halt
sole rodu Halt
b P Low power consumption
OObsolete 8.2
Slow mode
This mode has two targets:
● To reduce power consumption by decreasing the internal clock in the device
● To adapt the internal clock frequency (fCPU) to the available supply voltage.
Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables
slow mode.
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