ST7FLUS5MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLUS5MCE
STMicroelectronics
'ST7FLUS5MCE' PDF : 124 Pages View PDF
Power saving modes
ST7LUS5, ST7LU05, ST7LU09
8.4.1 Active halt mode
Active halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the HALT instruction when active halt mode is enabled.
The MCU can exit active halt mode on reception of a lite timer/auto-reload timer interrupt or
a reset.
● When exiting active halt mode by means of a reset, a 64 CPU cycle delay occurs. After
the start up delay, the CPU resumes operation by fetching the reset vector which woke
it up (see Figure 27).
● When exiting active halt mode by means of an interrupt, the CPU immediately resumes
operation by servicing the interrupt vector which woke it up (see Figure 27).
te Producctt((ss)) Caution:
When entering active halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In active halt mode, only the main oscillator and the selected timer counter (lite timer/auto-
reload timer) are running to keep a wake-up time base. All other peripherals are not clocked
except those which get their clock supply from another clock generator (such as external or
auxiliary oscillator).
As soon as active halt is enabled, executing a HALT instruction while the watchdog is active
does not generate a reset if the WDGHALT bit is reset. This means that the device cannot
spend more than a defined delay in this power saving mode.
sole rodu Figure 20. Active halt timing overview
- Ob te P Active
) le Run halt
64 CPU
cycle delay(1)
Run
uct(s Obso HALT
d - instruction
ro [active halt enabled]
Reset
or
interrupt
Fetch
vector
OObbssoolleettee PProduct(s) 1. This delay occurs only if the MCU exits active halt mode by means of a reset.
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