On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
11.5.2
11.5.3
Main features
● 10-bit conversion
● Up to 7 channels with multiplexed input
● Linear successive approximation
● Data register (DR) which contains the results
● Conversion complete status flag
● On/off bit (to reduce consumption)
The block diagram is shown in Figure 49.
Functional description
Analog power supply
VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to
device pin out description) they are internally connected to the VDD and VSS pins.
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
Figure 49. ADC block diagram
fCPU
DIV 2
0
1
DIV 4
1
0
SLOW
bit
fADC
EOC SPEED ADON 0
0 CH2 CH1 CH0 ADCCSR
3
AIN0
HOLD CONTROL
AIN1
ANALOG x 1 or
RADC
MUX
x8
ANALOG TO DIGITAL
CONVERTER
AINx
AMPSEL
bit
CADC
ADCDRH
D9 D8 D7 D6 D5 D4 D3 D2
ADCDRL
00
0
AMP
CAL
SLOW
AMP
SEL
D1
D0
Input voltage amplifier
The input voltage can be amplified by a factor of 8 by enabling the AMPSEL bit in the
ADCDRL register.
When the amplifier is enabled, the input range is 0 V to VDD/8.
104/166
Doc ID 8349 Rev 5