ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
Data register high (ADCDRH)
Read only
Reset value: xxxx xxxx (xxh)
7
0
D9
D8
D7
D6
D5
D4
D3
D2
● Bits 7:0 = D[9:2] MSB of analog converted value.
AMP control/data register low (ADCDRL)
Read / Write
Reset Value: 0000 00xx (0xh)
7
0
0
0
0
AMP CAL SLOW AMPSEL
D1
D0
Note:
Note:
● Bits 7:5 = Reserved. Forced by hardware to 0.
● Bit 4 = AMPCAL Amplifier Calibration Bit
This bit is set and cleared by software. User is suggested to use this bit to calibrate the
ADC when amplifier is ON. Setting this bit internally connects amplifier input to 0v.
Hence, corresponding ADC output can be used in software to eliminate amplifier-offset
error.
0: Calibration off
1: Calibration on (The input voltage of the amp is set to 0V).
It is advised to use this bit to calibrate the ADC when the amplifier is ON. Setting this bit
internally connects the amplifier input to 0v. Hence, the corresponding ADC output can be
used in software to eliminate an amplifier-offset error.
● Bit 3 = SLOW SLOW mode
This bit is set and cleared by software. It is used together with the SPEED bit to
configure the ADC clock speed as shown Table 46.
This bit is set and cleared by software.
Table 46.
ADC clock speed selection
fADC
fCPU/2
fCPU
fCPU/4
SLOW
0
0
1
SPEED
0
1
x
● Bit 2 = AMPSEL Amplifier selection bit
0: Amplifier is not selected
1: Amplifier is selected
● Bits 1:0 = D[1:0] LSB of analog converted value
When AMPSEL=1 it is mandatory that fADC be less than or equal to 2 MHz.
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Doc ID 8349 Rev 5
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