ST7LITE25F2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7LITE25F2
STMicroelectronics
'ST7LITE25F2' PDF : 170 Pages View PDF
On-chip peripherals
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
11.5.4
Low power modes
Table 44. Low power modes effects
Mode
Description
WAIT
HALT
No effect on A/D Converter
A/D Converter disabled.
After wakeup from HALT mode, the A/D Converter requires a stabilization time
tSTAB (see Electrical Characteristics) before accurate conversions can be
performed.
Note:
11.5.5
11.5.6
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
Interrupts
None.
Register Description
Control/status register (ADCCSR)
Read/Write (Except Bit 7 read only)
Reset Value: 0000 0000 (00h)
7
EOC
SPEED ADON
0
CH3
CH2
CH1
0
CH0
● Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by software reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete.
● Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used together with the SLOW bit to
configure the ADC clock speed. Refer to the table in the SLOW bit description.
● Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on.
● Bits 4:3 = Reserved. Must be kept cleared.
● Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
Table 45. Channel selection bits
Channel pin(1)
AIN0
AIN1
CH2
0
0
CH1
0
0
CH0
0
1
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Doc ID 8349 Rev 5
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