STLC1502 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC1502' PDF : 81 Pages View PDF
STLC1502
When the master device transmits data to a slave device via SMO pin, the slave device responds by send-
ing data to the master device to the SMI. This implies full duplex transmission with both data out and data
in synchronized with the same clock signal (which is provided by the master device via the SCK pin).
Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-
empty and receiver-full bits. A status flag is used to indicate that the I/O operation is complete.
The MSB is transmitted first.
Four possible data/clock timing relationships may be chosen.
7.5.2 Programming procedure
The SPI interface contains 3 dedicated registers:
• A Control Register (CR)
• A Status Register (SR)
• A Data Register (DR)
Check the register description section for bits position and functions.
Select the SPR0 & SPR1 bits to define the serial clock baud rate.
Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the
serial clock.
The transmit sequence begins when a byte is written in the DR register. The data byte is parallely loaded
into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the
SMO pin most significant bit first. When data transfer is complete:
The SPIF bit is set by hardware
.An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SR register while the SPIF bit is set
2. A read to the DR register.
Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.
7.5.3 Data Transfer Format
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in se-
rially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses.
Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred.
The combination between the CPOL and CPHA (clock phase) bits selects the data capture clock edge.
The master device applies data to its SMO pin before the capture clock edge.
CPHA bit is set:
The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set)
is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition.
CPHA bit is reset
The first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit
capture strobe. Data is latched on the occurrence of the first clock transition.
The slave select signal is necessary in case more than one slave devices are connected on the seral bus.
The slave select can be generated with a GPIO pin.
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